Verilog for digital design
Service Times: 9am and 10:30am
6399 North Wells Road, Bigtownville, CO 32748
  • Loading

Verilog for digital design

Email Print Export to ical format


Academy of Management & Science (AMS)
House # 89/E, Road # 13/C, Block # E, Banani, Dhaka 1213, Bangladesh
Telephone: +880 (2) 9891190, +880 (2) 8836875, Cell No: (88) 01680878839, (88) 01193070284

Resource Person

Khondakar Mujtaba is a Processor/ASIC design Engineer from Silicon valley, California, USA with extensive background in various sectors of semiconductor industry. He has more than 12 years of professional experience in broad area of microprocessor design, verification, synthesis, micro-architecture, low power/ high speed logic design, simulation, debug and timing closure. He was awarded US patent for innovation in the field of computer architecture.

Workshop Details

PowerPoint Presentation, Interactive Lecture, Lab work, Question and Answer session. Instructor-led course that uses a combination of presentation lectures and question and answer sessions, to discuss attendees

Who Can Attend

1. Undergraduate EEE and CSE student who will use Verilog for digital design as part of the class work or thesis. 
2. Post-graduate students who wants do research and study in digital design and computer architecture.
3. Professional who wants to build the foundation of RTL to work in the field of VLSI, FPGA/PLD or ASIC design and verification.

Engineering students and professionals who have background in:

  • Digital components (AND, XOR, MUX, Flip-Flop,..)
  • Simple computer architectures (ALU, State machine,.. )
  • Basic UNIX/ Linux knowledge is required for Lab work.




Verilog for digital design


This course is intended for the beginner’s level Verilog users. The course focuses on language aspects of Verilog HDL.  Students will be exposed basic Verilog constructs and modeling techniques, and the necessary knowledge to write small models and run simulations.


1. Undergraduate EEE and CSE student who will use Verilog for digital design as part of the class work or thesis.


20 Hours Lecture & 30 Hours Priject

Course Objectives:

This is a introductory Verilog course
• Using Verilog for digital design.
• HDL modeling designs for simulation.
• HDL Modeling designs for synthesis

Course Details:

Section 1: Digital Abstraction

Introduction to Verilog HDL modeling.

  • Lab1

Section 2: Verilog syntax and semantics

  • Lab2

Section 3: Combinational logic.

  • Lab3

Section 4: Sequential logic.

  • Lab4

Section 5: Finites State Machines.

  • Lab5

Training Calendar

<<  January  2018  >>
 S  M  T  W  T  F  S 
   1  2  3  4  5  6
  7  8  910111213


AMS Campus Facilities

  • Two Air conditioned seminar halls with projector & audio system [Maximum Capacity up to 50 persons] including video recording capacity.
  • Two different PC Labs (Air conditioned)
  • Centralized server
  • Internet / WIFI facilities
  • Practice facilities in LABS
  • Online Exam Centre
  • Cafeteria & Own cook facility
  • Large lobby with natural surroundings
  • Huge Parking Space
  • Waiting Lounge
  • Distance education facilities
  • Printer, Scanner etc logistics facilities
  • Special Guest Room
  • Registration Booth Arrangement Space
  • 3 Star Accommodation arrangements for foreign guests on demand in walking distance from the center.
    ………and many more

Contact AMS

Academy of Management & Science (AMS)
House #450, Road # 31, New DOHS,Mohakhali, Dhaka-1206, Bangladesh
Cell No: (88) 01616004108
Email: This email address is being protected from spambots. You need JavaScript enabled to view it.

Academy Location